Parallel Architecture for the Solution of Linear Equations Systems Based on Division Free Gaussian Elimination Method Implemented in FPGA

This paper presents a parallel architecture for the solution of linear equations systems based on the Division Free Gaussian Elimination Method. This architecture was implemented in a Field Programmable Gate Array (FPGA). The division-free Gaussian elimination method was integrated in identical processors in a FPGA Spartan 3 of Xilinx. A top-down design was used. The proposed architecture can handle IEEE 754 single and double precision floating-point data and the architecture was implemented in 240 processors. Also, an algorithmic complexity of O(n) was obtained using a n processors scheme that perform the solution of the linear equations. Moreover, the parallel division-free Gaussian elimination method, the architecture ́s data distribution and the internal processor-element (PE) architecture are presented. Finally, this paper presents the obtained simulation results and synthesis of the modules designed in very high-speed integrated circuit hardware description language (VHDL) using 40 and 100 Mhz frequencies. Key-Words: Field Programmable Gate Array (FPGA), Parallel Processing, Parallel Architectures, linear systems equations, Division Free Gaussian elimination Method.